Fifty years of Semicon Europa set a fitting backdrop for a conversation that feels both celebratory and unsentimental about the state of advanced packaging in Europe. We walk the floor in Munich and pull together a story that spans chemical metrology, panel plating, glass substrates, thermal materials, logistics resilience, and the push from R&D to production—plus a heartfelt goodbye.

Dena Mitchell, Nova opens the curtain on chemical metrology for electroplating, showing how bath health drives TSV fill, hybrid bond grain structure, and environmental wins through longer bath life. Sally Ann Henry, ACM Research, explains why horizontal panel electroplating can deliver better uniformity than vertical as panel-level packaging grows. Thomas Uhrmann, EV Group zooms out to the strategy: Europe’s strength in pilot lines and research consortia, the urgency to materialize large-scale packaging fabs, and how the EU Chips Act is knitting packaging into every node from photonics to logic.

Henkel's Ram Trichur takes on thermals, from kilowatt-class data center processors with backside power delivery to mobile’s shift from package-on-package to side-by-side for exposed die cooling, and the heat challenges inside HBM stacks. Comet's Isabella Drolz steps into glass panel territory with TGV inspection at 610 x 610 mm, aligning tools, standards, and timelines toward late-decade ramps. Martin Wynaendts van Resandt explains how
Lab14 brings agility with direct-write lithography for large substrates and optical interconnect masters—speeding iteration and trimming mask overhead as co-packaged optics advances. Jim Garstka, Shellback Semiconductor, talks about its Hydrozone product that is finding traction in photo mask cleaning.

We also get practical about moving all this innovation: Barry O'Dowd and Robin Knopf, of Kuehne+Nagel, detail how Europe’s packaging supply chains remain global, and how sea-air blends can cut cost and time for non-sensitive, high-volume flows while building resilience against disruptions. ASE's Patricia MacLeod, Christophe Zinck, and Bradford Factor tie it together with automotive realities—centralized compute, heterogeneous integration, reliability constraints—and the enduring role of MEMS and sensors to feed the brain of the car.

It’s a grounded, forward-looking journey through the technologies and decisions that will determine whether Europe turns its R&D leadership into production momentum. Listen for clear takeaways, candid perspectives, and a final toast to the community that made the 3D InCites Podcast possible.

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Europe’s chip future is being built in real time, and the view from Munich is electric. We sit down with IMEC’s leadership and ESMC’s founding CEO to unpack how pilot lines, a major Dresden fab, and the EU Chips Act are reshaping the continent’s strategy—from research to high-volume manufacturing. Along the way, we track the evolution of Semicon Europa over 50 years, from a supplier-centric expo to a convening force that brings equipment makers, materials leaders, device companies, and end users into one space.

Our guests open the hood on what resilience actually looks like: a 28 nm to 12 nm FinFET roadmap with integrated RRAM for microcontrollers, a half‑million‑wafers‑per‑year target, and a hiring plan that scales with purpose-built training in Dresden and Taiwan. On the R&D front, IMEC’s expanded pilot line infrastructure—fueled by multi‑billion‑euro investment—helps Europe retain technology leadership while translating breakthroughs into products. We also examine advanced packaging, where 3D integration and chiplet architectures blur the line between front end and back end and create fresh opportunities for automotive and industrial electronics.

The conversation gets candid on sovereignty versus interdependence. Full autarky is a myth; durable relevance comes from global collaboration, reverse dependencies, and focus on areas where Europe is indispensable—lithography, metrology, materials, and increasingly packaging and system design. We talk talent, too: why workforce visibility, skills pipelines, and on-the-job training will determine whether ambitious ramps hit their marks. If you care about semiconductors, policy, and the future of manufacturing in Europe, this is your inside track.

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A crowded server board with ten thousand parts doesn’t forgive sloppy inspection—and neither do pricey GPUs and chiplets. From the floor of Productronica in Munich, we dig into how automated optical inspection keeps advanced packages honest once they hit the PCB line, where solder quality, coplanarity, and sheer component variety can make or break yield. Vidya Vijay from Nordson Test & Inspection joins us to unpack why AOI remains the fastest path to actionable insight, when X‑ray is the smarter choice, and how new sensor design changes the game for reflective, high‑mix assemblies.

We explore the real pain points engineers face today: shiny dies that confuse cameras, BGAs packed with I/O where hidden defects hide under the body, and miniature passives that crowd tight keep‑outs. Vidya explains how three‑phase profilometry creates true 3D height maps by projecting fringe patterns and reading them from multiple angles, enabling precise checks for corner fill, underfill, and coplanarity. We also get into multi‑reflection suppression, Nordson’s approach to filtering glare and ghost images so the system sees the joint, not the noise. With true RGB on side cameras and higher resolution, AOI can now pick out tiny solder balls and subtle surface issues at speed—fuel for stronger AI autoprogramming and more reliable defect classification.

If throughput is king, data is queen. We talk about closing the loop from inspection back to the line to prevent bad lots—flagging stencil drift, placement offsets, and paste issues before they explode into scrap. Then we spotlight Nordson's launched SQ5000 Pro: faster cycle times, a wider field of view, and configurable 7 µm or 10 µm sensors designed for modern PCBA demands. Whether you’re chasing yield on high‑value GPUs or balancing AOI with AXI on dense boards, this conversation offers a practical roadmap for choosing the right tool, tackling reflectivity, and using insight to drive predictable quality.

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Want a candid look at how women build durable careers in one of the world’s toughest industries? We sit down with three semiconductor leaders - Nitza Basoco, Anne Meixner and Julia Freer - who share how early encouragement, gritty problem solving, and clear communication turned curiosity into impact. From summer jobs at national labs and early days at IBM to leading operations, test, and sustainability initiatives, their stories show why diverse voices aren’t just nice to have—they’re a competitive advantage.

We dig into the real moments: being the only woman in a test engineering group, pushing for inclusive language that actually changes culture, and navigating career pivots to balance family, flexibility, and ambition. You’ll hear how mentorship and sponsorship differ—and why you need both—plus specific tactics to make them work inside fast-moving chip companies. One unforgettable segment starts with a five-minute crash-and-burn presentation and becomes a two-year, teamwide communication overhaul that turns shy engineers into confident presenters ready for conferences and boardrooms.

Across materials science, advanced packaging, test and inspection, and sustainability, the thread is clear: communication is a core engineering skill. Writing reflective status reports, designing slides for decisions, and telling a tight technical story can accelerate yield improvements, align manufacturing and supply chain, and win executive support. We also tackle today’s DEI headwinds with a practical lens—keep the pipeline alive, promote from within, and build programs that outlast policy shifts. The conversation closes with why their new book matters: ordinary, relatable role models who show many valid paths into STEM and semiconductors.

Learn more about the book, Empowering Women in STEM.

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Power electronics are quietly rewriting the rules of energy use—from the range of your EV to the efficiency of a hyperscale data center. Françoise sits down with Henkel’s Ram Trichur to unpack what’s driving the $67.5B surge in power semiconductors and why the move to wide bandgap materials like silicon carbide and gallium nitride is such a big deal.

We break down the real differences between logic and power devices, then dive into where innovation is happening right now: die attach materials, thermal pathways, and manufacturing processes that can keep up with higher power densities. Ram explains why traditional wirebond packaging remains dominant in power, even as modules climb from 400 V to 800 V and beyond. You’ll learn how the industry is moving from solder to silver sintering for performance, and why copper-based sintering may be the breakthrough that balances cost, reliability, and manufacturability.

From discrete devices to full power modules, we explore the challenges of thinner die, copper leadframes, backside metallization compatibility, and bond line control. Ram shares Henkel’s roadmap for pressure-assisted copper sintering at lower temperatures and pressures in nitrogen, the multi-year qualification path customers expect, and how early sampling shortens time to scale. If you care about EV range, charger efficiency, industrial uptime, or greener data centers, this conversation connects the dots between materials science, packaging engineering, and system-level performance.

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The floor in Phoenix was packed, and so were the ideas. We sat down with innovators across the stack—equipment makers, metrology experts, logistics strategists, and software leaders—to map the real state of advanced packaging and what it takes to build, measure, move, and power tomorrow’s chips.

EV Group kicked things off with a candid look at die-to-wafer realities: activation on film frame, then 100% overlay metrology that measures tens of thousands of points per hour so every die and corner is verified. They also unveiled LithoScale XT, a fully digital, maskless lithography system printing 300 mm at 60 wph—perfect for massive AI dies and fast design turns.

Lab14 widened the frame with a portfolio approach: direct-write lithography, single-wafer processing, data prep, and analysis tools working as a coordinated line, with data sharing and AI feedback baked in.

Resilience and regionalization came to life through Kuehne+Nagel’s on-the-ground view: supplier clustering near fabs, cross-border trucking, time-critical services, and 4PL integration that gives real-time visibility and smarter capacity planning.

ERS showed where throughput meets cost: photothermal debonding with lower stress and reusable glass carriers, demo centers in Taiwan (and planned in North America), plus surge demand for warpage repair as volumes rise.

Process control is moving into packaging with front-end rigor. Nova detailed metrology for hybrid bonding, chemistry monitoring of plating baths, X-ray and XPS/SIMS material insights, and the handling know-how to measure framed wafers and panels reliably.

Nordson Test & Inspection highlighted AI-driven inspection, ultra-fast acoustic scanning, automated X-ray metrology, and sensor wafers that cut tool downtime and sharpen process windows. Comet showcased its CT and CA20 upgrades for 3D IC and TSV analysis.

Power dominated the later conversations. Siemens argued we need to design for energy from the chip through the blade, rack, and data center, simulating real workloads and cooling to slash gigawatts—then extend that thinking into the fab, where optimizing chillers and facilities already saves serious money.

Onto Innovation brought it home with execution: the PACE Center now hosts partners’ tools, accelerating experiments for glass, TGV, and panel processes without waiting on public funds.

If you care about hybrid bonding, maskless lithography, CT for 3D ICs, panel-scale packaging, or cutting AI’s energy bill, this one is dense with takeaways and hard truths. Subscribe, share with a colleague who lives in the fab or data center, and leave a review telling us which insight you’ll act on first.

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A nationwide talent engine for chips is taking shape—and it’s built to scale. Recorded live at SEMICON West in Phoenix, we sit down with SEMI Foundation leaders to unpack the National Network for Microelectronics Education, a hub-and-node model designed to align schools, employers, and workforce systems. Backed by CHIPS Act funding through the National Science Foundation, NNME will fund multi-state regional nodes that modernize curricula, streamline upskilling, and share proven playbooks across the country. We also unveil the refreshed Chip Path portal, which maps your skills and interests to real jobs in fabs, equipment, and materials, and we highlight SEMI-Quest, a hands-on STEM experience designed to spark early curiosity about microelectronics.

Then we turn to sustainability where momentum is accelerating. The Semiconductor Climate Consortium has grown past 100 members and is shifting from baselines to projects that deliver measurable impact. We explore how the Energy Collaborative pushes for policy that opens affordable renewable power, while SCC advances user-side strategies—better emissions accounting, renewable procurement models, and fab energy efficiency. A core challenge emerges: hyperscalers often target net zero by 2030, while many chipmakers point to 2050. We dig into how coordinated innovation, shared standards, and advocacy can close that 20-year gap.

AI’s energy appetite raises the stakes, so we tackle both sides of the equation: adding clean capacity where it matters most and designing for lower power at the chip and fab level. From global cooperation across APAC, EU, and the U.S. to practical ways individuals and companies can act now, the throughline is collaboration with urgency. Ready to find your role in the future of chips—whether building skills, hiring smarter, or decarbonizing faster? Subscribe, share this episode with your team, and leave a review to help more people find these insights.

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We recorded live at IMAPS with Siemens, ACM Research, Shellback Semiconductor, DECA, Nordson Electronic Solutions, and VIEW Micro Metrology to explore how AI demand, chiplets, and panels are reshaping advanced packaging. We dig into 3D BLOX, thermal and test roadblocks, green chemistries, metrology at scale, and why the back end now leads innovation. Listen to learn about:

• The Siemens–ASE collaboration on 3D BLOX models and VIPACK workflows
• Interoperable YAML-based packaging definitions moving toward IEEE standard
• 3D stacking to cut picojoules per bit amid thermal and test limits
• Panel-level packaging economics, sizes, and lack of standards
• ACM Research updates in copper plating, bevel clean, frame clean, and compound deplating
• Batch spray versus single wafer trade-offs at Shellback Semiconductor
• HydrOzone green strip replacing legacy NMP in select flows
•The DECA–SST deal for NVM chiplet package and SoC disaggregation
• Nordson Electronic Solutions' panel strategy, IntelliJet 1.1, Vantage platform, and warpage control
• VIEW Micro Metrology's high-throughput telecentric metrology across wafers and large panels

Learn more at imaps.org

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